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ispgal 22lv10 in-system programmable low voltage e 2 cmos pld generic array logic 1 features in-system programmable ieee 1149.1 standard tap controller port programming 4-wire serial programming interface minimum 10,000 program/erase cycles high performance e 2 cmos technology 4 ns maximum propagation delay fmax = 250 mhz 3 ns maximum from clock input to data output ultramos advanced cmos technology 3.3v low voltage 22v10 architecture jedec-compatible 3.3v interface standard 5v tolerant inputs and i/o i/o interfaces with standard 5v ttl devices active pull-ups on all logic input and i/o pins compatible with standard 22lv10/22v10 devices function/fuse-map compatible with 22lv10/22v10 devices parametric compatible with 22lv10 ? 2 cell technology in-system programmable logic 100% tested/100% yields high speed electrical erasure (<100ms) 20 year data retention applications include: dma control state machine control high speed graphics processing software-driven hardware configuration electronic signature for identification programmable and-array (132x44) i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q tdo tdi tms tck i/clk i i i i i i i i i i reset preset 8 10 12 14 16 16 14 12 10 8 olmc olmc olmc olmc olmc olmc olmc olmc olmc olmc programming logic i copyright ?1999 lattice semiconductor corp. all brand or product names are trademarks or registered trademarks of their respec tive holders. the specifications and information herein are subject to change without notice. lattice semiconductor corp., 5555 northeast moore ct., hillsboro, oregon 97124, u.s.a. december 1999 tel. (503) 681-0118; 1-888-isp-plds; fax (503) 681-3037; http://www.latticesemi.com plcc 228 tck i/clk i i i i i i i i tms tdo tdi gnd i i i i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q vcc i/o/q i/o/q i/o/q 426 25 19 18 21 23 16 14 12 11 9 7 5 vcc i/o/q i/o/q i/o/q i/o/q i/o/q tdo i/o/q i/o/q i/o/q i/o/q i/o/q i tdi tck i/clk i i i i i tms i i i i i gnd 1 7 14 28 22 15 ispgal 22lv10 top view ssop ispgal22lv10 top view isp22lv_06 description the ispgal22lv10 is manufactured using lattice semiconductor's advanced 3.3v e 2 cmos process, which combines cmos with electrically erasable (e 2 ) floating gate technology. the ispgal22lv10 can interface with both 3.3v and 5v signal levels. the ispgal22lv10 is fully function/fuse map compatible with the gal 22lv10 and gal22v10. further, the ispgal22lv10 is para- metric compatible with the gal22lv10. the ispgal22lv10 also shares the same 28-pin plcc package pin-out as the gal22lv10. unique test circuitry and reprogrammable cells allow complete ac, dc, and functional testing during manufacture. as a result, lat- tice semiconductor delivers 100% field programmability and func- tionality of all gal products. in addition, 10,000 erase/write cycles and data retention in excess of 20 years are specified. functional block diagram pin configuration new 4ns speed grade
specifications ispgal22lv10 2 commercial grade specifications ) s n ( d p t) s n ( u s t) s n ( o c t) a m ( c c i# g n i r e d r oe g a k c a p 433 0 3 1j l 4 - 0 1 v l 2 2 l a g p s ic c l p d a e l - 8 2 l 4 - 0 1 v l 2 2 l a g p s ik d a e l - 8 2p o s s 55 . 35 . 30 3 1j l 5 - 0 1 v l 2 2 l a g p s ic c l p d a e l - 8 2 l 5 - 0 1 v l 2 2 l a g p s ik d a e l - 8 2p o s s 5 . 755 0 3 1j l 7 - 0 1 v l 2 2 l a g p s ic c l p d a e l - 8 2 l 7 - 0 1 v l 2 2 l a g p s ik d a e l - 8 2p o s s 0 17 5 . 60 3 1j l 0 1 - 0 1 v l 2 2 l a g p s ic c l p d a e l - 8 2 - 0 1 v l 2 2 l a g p s i0 1lk d a e l - 8 2p o s s 5 10 18 0 3 1j l 5 1 - 0 1 v l 2 2 l a g p s ic c l p d a e l - 8 2 - 0 1 v l 2 2 l a g p s i5 1lk d a e l - 8 2p o s s blank = commercial i = industrial grade package power l = low power speed (ns) xxxxxxxx xx x x x device name _ j = plcc k = ssop ispgal22lv10 ordering information part number description industrial grade specifications ) s n ( d p t) s n ( u s t) s n ( o c t) a m ( c c i# g n i r e d r oe g a k c a p 5 . 755 0 6 1i j l 7 - 0 1 v l 2 2 l a g p s ic c l p d a e l - 8 2 l 7 - 0 1 v l 2 2 l a g p s ii kd a e l - 8 2p o s s 0 17 5 . 60 6 1i j l 0 1 - 0 1 v l 2 2 l a g p s ic c l p d a e l - 8 2 - 0 1 v l 2 2 l a g p s i0 1l i kd a e l - 8 2p o s s 5 10 18 0 6 1i j l 5 1 - 0 1 v l 2 2 l a g p s ic c l p d a e l - 8 2 - 0 1 v l 2 2 l a g p s i5 1l i kd a e l - 8 2p o s s
specifications ispgal22lv10 3 ispgal22lv10 output logic macrocell (olmc) each of the macrocells of the ispgal22lv10 has two primary func- tional modes: registered, and combinatorial i/o. the modes and the output polarity are set by two bits (s0 and s1), which are nor- mally controlled by the logic compiler. each of these two primary modes, and the bit settings required to enable them, are described below and on the following page. registered in registered mode the output pin associated with an individual olmc is driven by the q output of that olmc s d-type flip-flop. logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). output tri-state control is available as an in- dividual product-term for each olmc, and can therefore be defined by a logic equation. the d flip-flop s /q output is fed back into the and array, with both the true and complement of the feedback available as inputs to the and array. note: in registered mode, the feedback is from the /q output of the register, and not from the pin; therefore, a pin defined as reg- istered is an output only, and cannot be used for dynamic i/o, as can the combinatorial pins. combinatorial i/o in combinatorial mode the pin associated with an individual olmc is driven by the output of the sum term gate. logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). out- put tri-state control is available as an individual product-term for each output, and may be individually set by the compiler as either on (dedicated output), off (dedicated input), or product-term driven (dynamic i/o). feedback into the and array is from the pin side of the output enable buffer. both polarities (true and inverted) of the pin are fed back into the and array. the ispgal22lv10 has a variable number of product terms per olmc. of the ten available olmcs, two olmcs have access to eight product terms (pins 17 and 27), two have ten product terms (pins 18 and 26), two have twelve product terms (pins 19 and 25), two have fourteen product terms (pins 20 and 24), and two olmcs have sixteen product terms (pins 21 and 23). in addition to the product terms available for logic, each olmc has an additional product-term dedicated to output enable control. the output polarity of each olmc can be individually programmed to be true or inverting, in either combinatorial or registered mode. this allows each output to be individually configured as either active high or active low. the ispgal22lv10 has a product term for asynchronous reset (ar) and a product term for synchronous preset (sp). these two product terms are common to all registered olmcs. the asynchro- nous reset sets all registers to zero any time this dedicated product term is asserted. the synchronous preset sets all registers to a logic one on the rising edge of the next clock pulse after this product term is asserted. note: the ar and sp product terms will force the q output of the flip-flop into the same state regardless of the polarity of the output. therefore, a reset operation, which sets the register output to a zero, may result in either a high or low at the output pin, depending on the pin polarity chosen. ar sp d q q clk 4 to 1 mux 2 to 1 mux output logic macrocell (olmc) output logic macrocell configurations
specifications ispgal22lv10 4 active high active low active high active low s 0 = 1 s 1 = 1 s 0 = 0 s 1 = 1 s 0 = 0 s 1 = 0 s 0 = 1 s 1 = 0 ar sp d q q clk ar sp d q q clk registered mode combinatorial mode
specifications ispgal22lv10 5 plcc & ssop package pinout 2 26 olmc s0 5810 s1 5811 0440 . . . . 0880 3 asynchronous reset (to all registers) 0 4 8 1216202428323640 synchronous preset (to all registers) 12 0000 5764 0044 . . . 0396 27 s0 5808 s1 5809 25 olmc s0 5812 s1 5813 0924 . . . . . 1452 4 5 6 24 olmc s0 5814 s1 5815 1496 . . . . . . 2112 23 olmc s0 5816 s1 5817 2156 . . . . . . . 2860 21 olmc s0 5818 s1 5819 2904 . . . . . . . 3608 20 olmc s0 5820 s1 5821 3652 . . . . . . 4268 olmc s0 5822 s1 5823 4312 . . . . . 4840 10 19 18 olmc s0 5824 s1 5825 4884 . . . . 5324 11 5368 . . . 5720 17 olmc s0 5826 s1 5827 9 7 13 16 8 10 14 16 12 12 16 14 10 8 olmc electronic signature 5828, 5829 ... ... 5890, 5891 l s b m s b byte 7 byte 6 byte 5 byte 4 byte 2 byte 1 byte 0 byte 3 ispgal22lv10 logic diagram/jedec fuse map
specifications ispgal22lv10 6 specifications ispgal22lv10 1) the leakage current is due to the internal pull-up resistor on all pins. see input buffer section for more information. 2) one output at a time for a maximum duration of one second. vout = 0.5v was selected to avoid test problems caused by tester ground degradation. characterized but not 100% tested. 3) typical values are at vcc = 3.3v and ta = 25 c commercial i cc operating power v il = 0v v ih = 3.0v unused inputs at v il 90 130 ma supply current f toggle = 1mhz outputs open v il input low voltage vss - 0.3 0.8 v v ih input or i/o high voltage 2.0 5.25 v i il 1 input or i/o low leakage current 0v v in v il (max.) -150 a i ih input or i/o high leakage current ( v cc-0.2)v v in v cc 10 a input or i/o high leakage current v cc v in 5.25v 2ma v ol output low voltage i ol = max. v in = v il or v ih 0.4 v i ol = 500 a v in = v il or v ih 0.2 v v oh output high voltage i oh = max. v in = v il or v ih 2.4 v i oh = -100 a v in = v il or v ih v cc-0.2v v i ol low level output current 8ma i ol-isp low level output current tdo 4ma i oh high level output current 8ma i oh-isp high level output current tdo 2ma i os 2 output short circuit current v cc = 3.3v v out = 0.5v t a = 25 c -30 -80 ma recommended operating conditions commercial devices: ambient temperature (t a ) ............................... 0 to 75 c supply voltage (v cc ) with respect to ground ......................... +3.0 to +3.6v industrial devices: ambient temperature (t a ) ............................ -40 to 85 c supply voltage (v cc ) with respect to ground ......................... +3.0 to +3.6v absolute maximum ratings (1) supply voltage v cc .................................... -0.5 to +4.6v input and i/o voltage applied ..................... -0.5 to +5.6v off-state output voltage applied ................ -0.5 to +4.6v storage temperature ................................. -65 to 150 c ambient temperature with power applied ......................................... -55 to 125 c 1.stresses above those listed under the absolute maximum ratings may cause permanent damage to the device. these are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). symbol parameter condition min. typ. 3 max. units dc electrical characteristics over recommended operating conditions (unless otherwise specified) industrial i cc operating power v il = 0v v ih = 3.0v unused inputs at v il 90 160 ma supply current f toggle = 1mhz outputs open
specifications ispgal22lv10 7 -5 min. max. specifications ispgal22lv10 -10 min. max. t pd 2 a input or i/o to comb. output 1 4 1 5 1 7.5 1 10 1 15 ns t co 2 a clock to output delay 1 3 1 3.5 1 5 1 6.5 8ns t cf 3 clock to feedback delay 2.5 2.5 2.5 2.5 2.5 ns t su setup time, input or fdbk before clk 3 3.5 5 7 10 ns t h hold time, input or fdbk after clk 0 0 0 0 0 ns a maximum clock frequency with 167 143 100 74 55.5 mhz external feedback, 1/(tsu + tco) f max 4 a maximum clock frequency with 182 166 133 105 80 mhz internal feedback, 1/(tsu + tcf) a maximum clock frequency with 250 200 166 111 83.3 mhz no feedback t wh 4 clock pulse duration, high 2 2.5 3 4 6 ns t wl 4 clock pulse duration, low 2 2.5 3 4 6 ns t en b input or i/o to output enabled 1 5 1 6 1 7.5 1 10 15 ns t dis c input or i/o to output disabled 1 5 1 6 1 7.5 1 10 15 ns t ar a input or i/o to asynch. reset of reg. 1 4.5 1 5.5 1 9 1 13 20 ns t arw asynchronous reset pulse duration 4.5 5.5 7 8 15 ns t arr asynch. reset to clk recovery time 3.5 4 5 8 10 ns t spr synch. preset to clk recovery time 3.5 4 5 10 10 ns -7 min. max. units param. test cond 1 . description symbol parameter typical units test conditions c i input capacitance 4 pf v cc = 3.3v, v i = 0v c i/o i/o capacitance 5 pf v cc = 3.3v, v i/o = 0v 1) refer to switching test conditions section. 2) minimum values for t pd and t co are not 100% tested but established by characterization. 3) calculated from f max with internal feedback. refer to fmax descriptions section. 4) refer to fmax descriptions section. characterized but not 100% tested. note: maximum clock input rise and fall time between 10% to 90% of vout = 2ns. com/ind com/ind com ac switching characteristics over recommended operating conditions capacitance (ta = 25 c, f = 1.0 mhz) -15 min. max. com/ind -4 min. max. com
specifications ispgal22lv10 8 input or i/o to output enable/disable registered output combinatorial output f max with feedback clock width t en t dis input or i/o feedback output clk (w/o fdbk) t wh t wl 1/ f max input or i/o feedback registered output clk valid input t su t co t h (external fdbk) 1/ f max clk registered feedback t cf t su 1/ f max (internal fdbk) registered output clk t arw t arr input or i/o feedback driving ar t ar asynchronous reset registered output clk input or i/o feedback driving sp t su t h t co t spr synchronous preset valid input input or i/o feedback t pd combinatorial output switching waveforms
specifications ispgal22lv10 9 f max with internal feedback 1/( t su+ t cf) note: t cf is a calculated value, derived by sub- tracting t su from the period of fmax w/internal feedback ( t cf = 1/ f max - t su). the value of t cf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. for example, the timing from clock to a combi- natorial output is equal to t cf + t pd. f max with no feedback note: f max with no feedback may be less than 1/ t wh + t wl. this is to allow for a clock duty cycle of other than 50%. register logic array t co t su clk note: f max with external feedback is cal- culated from measured t su and t co. f max with external feedback 1/( t su+ t co) clk register logic array t cf t pd register logic array clk t su + t h f max descriptions switching test conditions *c l includes test fixture and probe capacitance. test point z 0 = 50 ? , c l = 35pf* from output (o/q) under test +1.45v r 1 input pulse levels gnd to 3.0v input rise and fall times 1.5ns 10% 90% input timing reference levels 1.5v output timing reference levels 1.5v output load see figure output load conditions (see figure) test condition r 1 c l a50 ? 35pf b high z to active high at 1.9v 50 ? 35pf high z to active low at 1.0v 50 ? 35pf c active high to high z at 1.9v 50 ? 35pf active low to high z at 1.0v 50 ? 35pf
specifications ispgal22lv10 10 electronic signature an electronic signature (es) is provided in every ispgal22lv10 device. it contains 64 bits of reprogrammable memory that can contain user-defined data. some uses include user id codes, revision numbers, or inventory control. the signature data is always available to the user independent of the state of the security cell. the electronic signature is an additional feature not present in other manufacturers' 22v10 devices. to use the extra feature of the user-programmable electronic signature it is necessary to choose a lattice semiconductor 22v10 device type when com- piling a set of logic equations. in addition, many device programmers have two separate selections for the device, typically an ispgal22lv10 and a ispgal22lv10-ues (ues = user electronic signature) or ispgal22lv10-es. this allows users to maintain compatibility with existing 22v10 designs, while still having the option to use the gal device's extra feature. the jedec map for the ispgal22lv10 contains the 64 extra fuses for the electronic signature, for a total of 5892 fuses. however, the ispgal22lv10 device can still be programmed with a standard 22v10 jedec map (5828 fuses) with any qualified device programmer. security cell a security cell is provided in every ispgal22lv10 device to prevent unauthorized copying of the array patterns. once programmed, this cell prevents further read access to the func- tional bits in the device. this cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. the electronic signature is always available to the user, regardless of the state of this control cell. latch-up protection ispgal22lv10 devices are designed with an on-board charge pump to negatively bias the substrate. the negative bias is of sufficient magnitude to prevent input undershoots from causing the circuitry to latch. device programming the ispgal22lv10 device uses a standard 22v10 jedec fusemap file to describe the device programming information. any third party logic compiler can produce the jedec file for this device. in-system programmability the ispgal22lv10 device features in-system programmable technology. by integrating all the high voltage programming circuitry on-chip, programming can be accomplished by simply shifting data into the device. once the function is programmed, the non-volatile e 2 cmos cells will not lose the pattern even when the power is turned off. all necessary programming is done via four ttl level logic interface signals. these four signals are fed into the on-chip programming circuitry where a state machine controls the pro- gramming. the interface signals are test data in (tdi), test data out (tdo), test clock (tck) and test mode select (tms) control. for details on the operation of the internal state machine and programming of ispgal22lv10 devices please refer to the isp architecture and programming section in this data book. output register preload when testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. this is because certain events may occur during system operation that throw the logic into an illegal state (power-up, line voltage glitches, brown- outs, etc.). to test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. then the machine can be sequenced and the outputs tested for correct next state conditions. the ispgal22lv10 device includes circuitry that allows each registered output to be synchronously set either high or low. thus, any present state condition can be forced for test sequenc- ing. if necessary, approved gal programmers capable of executing test vectors perform output register preload automati- cally. input buffers ispgal22lv10 devices are designed with ttl level compatible input buffers. these buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar ttl devices. all input and i/o pins also have built-in active pull-ups. as a result, floating inputs will float to a ttl high (logic 1). however, lattice semiconductor recommends that all unused inputs and tri-stated i/o pins be connected to an adjacent active input, vcc, or ground. doing so will tend to improve noise immunity and reduce icc for the device. (see equivalent input and i/o schemat- ics on the following page.) typical input current -50.00 -40.00 -30.00 -20.00 -10.00 0.00 0.00 1.00 2.00 3.00 4.00 input voltage (volts) input current ( a)
specifications ispgal22lv10 11 vcc (min.) t pr internal register reset to logic "0" device pin reset to logic "1" t wl t su device pin reset to logic "0" vcc clk internal register q - output active low output register active high output register up, some conditions must be met to provide a valid power-up reset of the ispgal22lv10. first, the vcc rise must be monotonic. second, the clock input must be at static ttl level as shown in the diagram during power up. the registers will reset within a maximum of tpr time. as in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. the clock must also meet the minimum pulse width requirements. output input (vref = vcc) vcc pin vref tri-state control active pull-up circuit feedback (to input buffer) pin feedback data output (vref = vcc) vcc pin vcc vref active pull-up circuit esd protection circuit esd protection circuit vcc pin circuitry within the ispgal22lv10 provides a reset signal to all registers during power-up. all internal registers will have their q outputs set low after a specified time (tpr, 1 s max). as a result, the state on the registered output pins (if they are enabled) will be either high or low on power-up, depending on the programmed polarity of the output pins. this feature can greatly simplify state machine design by providing a known state on power-up. the timing diagram for power-up is shown above. because of the asynchronous nature of system power- power-up reset input/output equivalent schematics
specifications ispgal22lv10 12 ispgal22lv10: typical ac and dc characteristic diagrams normalized tpd vs vcc 0.85 0.9 0.95 1 1.05 1.1 1.15 1.2 3 3.15 3.3 3.45 3.6 supply voltage (v) normalized tpd rise fall normalized tco vs vcc 0.97 0.98 0.99 1 1.01 1.02 1.03 3 3.15 3.3 3.45 3.6 supply voltage (v) normalized tco rise fall normalized tsu vs vcc 0.8 0.9 1 1.1 1.2 3 3.15 3.3 3.45 3.6 supply voltage (v) normalized tsu rise fall normalized tpd vs temp 0.9 1 1.1 1.2 -55 -25 0 25 50 75 100 125 temperature (deg. c) normalized tpd rise fall normalized tsu vs temp 0.85 0.9 0.95 1 1.05 1.1 1.15 1.2 -55-25 0 25 50 75100125 temperature (deg. c) normalized tsu rise fall normalized tco vs temp 0.9 0.95 1 1.05 1.1 1.15 -55 -25 0 25 50 75 100 125 temperature (deg. c) normalized tco rise fall delta tpd vs # of outputs switching -0.4 -0.3 -0.2 -0.1 0 12345678910 number of outputs switching delta tpd (ns) rise fall delta tco vs # of outputs switching -0.4 -0.3 -0.2 -0.1 0 12345678910 number of outputs switching delta tco (ns) rise fall delta tpd vs output loading -4 0 4 8 12 16 0 50 100 150 200 250 300 output loading (pf) delta tpd (ns) rise fall delta tco vs output loading -4 0 4 8 12 16 0 50 100 150 200 250 300 output loading (pf) delta tco (ns) rise fall
specifications ispgal22lv10 13 ispgal22lv10: typical ac and dc characteristic diagrams vol vs iol 0 0.2 0.4 0.6 0.8 1 0 5 10 15 20 25 30 35 iol (ma) vol (v) voh vs ioh 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 0 5 10 15 20 ioh (ma) voh (v) voh vs ioh 2.8 2.85 2.9 2.95 3 3.05 0.00 1.00 2.00 3.00 4.00 5.00 ioh (ma) voh (v) normalized icc vs vcc 0.9 0.95 1 1.05 1.1 1.15 3 3.15 3.3 3.45 3.6 supply voltage (v) normalized icc normalized icc vs temp 0.8 0.9 1 1.1 1.2 -55-25 0 25 50 88100125 temperature (deg. c) normalized icc normalized icc vs freq 1 1.05 1.1 1.15 1.2 1.25 1.3 1 15255075100 frequency (mhz) normalized icc input clamp (vik vs iik) 0 10 20 30 40 50 60 -2.9 -2.3 -1.7 -1.1 -0.5 0 vik (v) iik (ma) delta icc vs vin (1 input) 0 1 2 3 4 5 6 7 8 9 10 00.511.522.533.544.55 vin (v) delta icc (ma)
specifications ispgal22lv10 14 notes

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